The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly concerns a manufacturing method and a structure of a semiconductor device which is allowed to have a high density by stacking a plurality of semiconductor chips.
In recent years, along with the miniaturization of semiconductor devices, semiconductor devices which are miniaturized virtually to a chip size have been developed. This miniaturized structure of the semiconductor device is referred to as the CSP (Chip Size Package) structure.
FIGS. 10(a) and 10(b) show examples of semiconductors having the CSP structure.
In the semiconductor device of the CSP structure as shown in FIG. 10(a), a semiconductor chip 50 is installed on a circuit substrate with its surface (hereinafter, referred to as xe2x80x9cactive facexe2x80x9d) having elements (not shown) such as transistors formed thereon facing up (face-up bonding). Electrodes, formed on the active face (hereinafter, referred to as plane electrodes 68 so as to distinguish them from protrusion electrodes), are connected to the circuit substrate 53 by using wires 58, that is, more specifically, to plane electrodes (not shown) of a wiring layer 54 formed on the circuit substrate 53. The connection between electrodes using the wires 58 of this type is generally referred to as wire bonding.
Here, in the Figures, reference numeral 60 represents an external terminal that is connected to the wiring layer 54 through a penetration hole 61 formed in the circuit substrate 53. The surface of the circuit substrate 53 on the side having the installed semiconductor chip 50, etc. is covered with coat resin 59.
In a semiconductor device of the CSP structure as shown in FIG. 10(b), the semiconductor chip 50 is packaged on the circuit substrate 53 with its active face facing down (facedown bonding). Protrusion electrodes 56 are formed on plane electrodes (not shown) formed on the active face so that the protrusion electrodes 56 are directly connected to plane electrodes (not shown) on the wiring layer 54. The connection of this type directly connecting electrodes is generally referred to as flip-chip bonding.
Moreover, in some constructions to be packaged on a portable information apparatus, etc., in an attempt to give xe2x80x9cadded valuexe2x80x9d and to further increase the capacity, a plurality of semiconductor chips are included in one package so as to increase the packaging density. In this case, in a multi-chip module in which a plurality of chips are simply placed two-dimensionally, it is not possible to form a semiconductor package that is smaller than the total area of the semiconductor chips.
In this attempt, a technique for further increasing the packaging density by installing a plurality of semiconductor chips in a laminated manner has been proposed. FIGS. 11(a) and 11(b) show such semiconductor devices of the CSP structure having laminated semiconductor chips.
In the semiconductor device of the CSP structure shown in FIG. 11(a), the first semiconductor chip 51 and the second semiconductor ship 52 are installed on a circuit substrate 53 in a laminated manner, and these are respectively connected to the circuit substrate 53 by means of wire bonding by means of wires 58 (Prior Art (1)).
In the semiconductor device of the CSP structure shown in FIG. 11(b), of the first semiconductor chip 51 and the second semiconductor chip 52 laminated on the circuit substrate 53, the upper second semiconductor chip 52 is connected to the circuit substrate 53 by means of wire bonding, and the lower first semiconductor chip 51 is connected thereto by means of flip-chip bonding (see Japanese Laid-Open Patent Application No. 47998/1993 (Tokukaihei 5-47998) (published on Feb. 26, 1993) and Japanese Laid-Open Patent Application No. 326710/1995 (Tokukaihei 7-326710) (published on Dec. 12, 1995: Prior Art (2)).
Moreover, as illustrated in FIG. 12, Japanese Laid-Open Patent Application No. 84128/1988 (Tokukaishou 63-84128) (published on Apr. 14, 1988) discloses a semiconductor device in which a connection system combining the wire bonding and flip-flop chip bonding is adopted in the same manner as Prior Art (2) and in which the upper second semiconductor chip 52 is set to be larger than the lower first semiconductor chip 51, and these chips are packaged on a circuit substrate 53xe2x80x2 such as a mother board (Prior Art (3)).
However, in these conventional structures, the size and combination of applicable semiconductor chips are limited, resulting in a problem of limited application.
Specifically, in Prior Art (1) shown in FIG. 11(a), in the case when the upper second semiconductor chip 52 is as large as, or larger than the lower first semiconductor chip 51, it is not possible to secure a space used for installing plane electrodes 68a on the active face of the first semiconductor chip 51. Therefore, it is not possible to use the second semiconductor chip 52 that is larger than the first semiconductor chip 51.
In the prior art (2) shown in FIG. 11(b), on the other hand, since the lower first semiconductor chip 51 is connected to the circuit substrate 53 by means of flip-chip bonding, the problem as explained in Prior Art (1) is not raised.
However, in Prior Art (2), the second conductor chip 52 is normally set to be smaller than, or as large as the first conductor chip 51. This is because when the upper second semiconductor chip 52 is made larger, it is not possible to carry out a stable wire bonding thereon. In other words, since no support exists below the plane electrodes 68 to which wires 58 of the second semiconductor chip 52 are connected, the second semiconductor chip 52 might be damaged due to an impact and a load at the time of wire bonding, or a sufficient load and ultrasonic waves might not be applied thereon.
Here, in Prior Art (3) shown in FIG. 12, although it has a construction in which the upper second semiconductor chip 52 is made larger, the plane electrodes 68 of the second semiconductor chip 52 are formed within the range of the lower first semiconductor chip 51 in a limited manner in order to stabilize the wire bonding.
This construction, which has the plane electrodes 68 placed apart from the edge of the second semiconductor chip 52, raises a problem in which elements on the periphery of the chip might be damaged or might contact the edge of the chip in a dicing process for dividing the wafer into semiconductor chips.
Therefore, it is not possible to adopt combinations in which either one of the chips is placed under the other with either of them sticking, such as a combination in which one of the chips virtually has a square shape with the other having a narrow rectangular shape.
Here, another technique is proposed in which a support member having the same thickness as the first semiconductor chip 51 is inserted to the lower portion of the second semiconductor chip 52 that is sticking out; however, this construction is not suitable because it is difficult to produce the support member having the same thickness with high precision and because complex processes cause high costs.
Moreover, even in the case when the upper second semiconductor chip 52 is smaller, if it is far smaller than the first semiconductor chip 51, these can not be combined. In other words, wires 58 become too long, causing wire flow and wire deformation. When an attempt is made to connect the wires 58 at positions on the wiring layer 54 as closely as possible to the first semiconductor chip 51, short-circuiting might occur due to contact with the edge of the first semiconductor chip 51. In order to avoid this problem, when the wires 58 are connected at positions far from the first semiconductor chip 51 on the wiring layer 54, the package size becomes larger.
The present invention relates to a semiconductor device for achieving a high density by laminating a plurality of semiconductor chips, and its objective is to provide a semiconductor device in which, even in the case when, from the semiconductor chips laminated on a circuit substrate, one portion of the semiconductor chip located on the other is protruding, wire bonding is preferably carried out by using an electrode placed at the protruding portion, and a manufacturing method for such a semiconductor device.
In order to achieve the above-mentioned objective, the manufacturing method of the semiconductor device of the present invention includes the steps of:
a) applying a bonding agent to a circuit substrate so as to connect a first semiconductor chip and the circuit substrate by means of flip-flop bonding through the bonding agent;
b) connecting a second semiconductor chip having a protruding portion protruding from the first semiconductor chip to the circuit substrate with a rear face thereof being bonded to a rear face of the first semiconductor chip by means of wire bonding at the protruding portion; and
c) forming a support portion for supporting the protruding portion by using one portion of the bonding agent.
In the above-mentioned method, the first semiconductor chip is connected to the circuit substrate by means of flip-chip bonding through the bonding agent. The second semiconductor chip is connected to the circuit substrate by wire bonding.
In a conventional manufacturing method for a semiconductor device, in the case of the application of a connecting system using the above-mentioned combination of flip-chip bonding and wire bonding, there have been limitations imposed on the size and shape of the first and second semiconductor chips.
First, in the conventional system, when chips and a circuit substrate are connected by using the above-mentioned connecting method in the case where the second semiconductor chip protrudes from the first semiconductor chip, the following problems arise:
Upon carrying out wire bonding at the portion of the second semiconductor chip protruding from the first semiconductor chip, the second semiconductor chip might be damaged due to its impact and load; therefore, in the conventional manufacturing method of the semiconductor device, wire bonding is carried out at positions that are supported by the first semiconductor chip and located inside the protruding portion of the second semiconductor chip so as to prevent damages to the second semiconductor chip. However, such a conventional method lengthens wires to be used in the connection, causing problems of wire flow and wire deformation.
Second, in the conventional method, in the case when one of two chips is far smaller than the other, the smaller has been used as the second semiconductor chip; however, this case also has lengthened the wires, causing problems of wire flow and wire deformation, and failing to properly use such a combination of the chips.
In contrast, in the above-mentioned method of the present invention, one portion of the bonding agent used for the connection to the first semiconductor chip is utilized to form a support portion for supporting the protruding portion of the second semiconductor chip.
Consequently, since the protruding portion of the second semiconductor chip is supported by the support portion so that even the protruding portion is subjected to a wire bonding process stably without damages to the second semiconductor chip.
Moreover, even in the case when one of two chips is far smaller than the other, it is possible to use the smaller not as the second semiconductor chip, but rather as the first semiconductor chip; therefore, it becomes possible to avoid conventional problems of wire flow and wire deformation.
As described above, in the manufacturing method of the semiconductor device of the present invention, since no limitation is imposed on the size and shape of the first and second semiconductor chips, it is possible to apply combinations of chips having various sizes and shapes, such as a combination of a square chip and a rectangular chip, and consequently to widen the degree of freedom in designing.
Moreover, in the manufacturing method of the semiconductor device of the present invention, one portion of the bonding agent used for connecting the first semiconductor chip is utilized to form the support portion, without the need for separately installing a new member; thus, it becomes possible to prevent an increase in the number of processes as well as costs.
Furthermore, in order to achieve the above-mentioned objective, the semiconductor device of the present invention is provided with:
a first semiconductor chip that is connected to the circuit substrate through a bonding agent with an active face facing the circuit substrate;
a second semiconductor chip having a protruding portion protruding from the first semiconductor chip with the rear face thereof being bonded to the rear face of the first semiconductor chip, the protruding portion being connected to the circuit board by means of wire bonding; and
a support portion for supporting the protruding portion, the support portion being formed by one portion of the bonding agent.
With the above-mentioned construction, the first and second semiconductor chips are joined to each other with their rear faces being bonded to each other, and respectively connected to the circuit substrate. The connection between the second semiconductor chip and the circuit substrate is made at the protruding portion protruding from the first semiconductor chip.
In other words, different from the conventional construction, the connection through the wires is not made on the portion of the second semiconductor chip supported by the first semiconductor chip; however, this wiring portion is supported by the support portion formed by one portion of the bonding agent so that it becomes possible to carry out a better wire bonding process without causing damages to the second semiconductor chip, and also to eliminate the necessity of carrying out wire bonding at the portion of the second semiconductor chip supported by the first semiconductor chip. Thus, it is possible to avoid the conventional problem of wire deformation.